Recently, the magnetic random access memory (hereinafter called MRAM) including magnetoresistive effect elements arranged in a matrix is noted as a rewritable nonvolatile memory. The MRAM utilizes combinations of the magnetization directions of two magnetic layers to memorize information and detects resistance changes (i.e., current or voltage changes) between a resistance given when the magnetization directions of the magnetic layers are parallel with each other and a resistance given when the magnetization directions of the magnetic layers are antiparallel with each other to thereby read the memorized information.
As one of the magnetoresistive effect elements forming the MRAM, magnetic tunnel junction (hereinafter called MTJ) element is known. The MTJ element includes two ferromagnetic layers laid one on another with a tunnel insulating film formed therebetween and utilizes the phenomena that the tunnel current flowing between the ferromagnetic layers via the tunnel insulating film changes based on relationships between the magnetization directions of the two ferromagnetic layers. That is, the MTJ element has low element resistance when the magnetization directions of the two ferromagnetic layers are parallel with each other and when they are antiparallel with each other, the MTJ element has high element resistance. These two states are related to data “0” and data “1” to use the MTJ element as a memory element. The MTJ element, which is thus a memory element utilizing changes of the element resistance must convert resistance changes to voltages or currents to read the memorized information.
The method for reading the conventional magnetic memory device will be explained with reference to FIGS. 18 to 20.
The magnetic memory device shown in FIG. 18 has a memory cell 100 formed of one select transistor 102 and one MTJ element 104 (1T-1MTJ type). The select transistor 102 and the MTJ element 104 are serially connected. The end on the side of the MTJ element 104 is connected to a current source 106, and the end on the side of the select transistor 102 is grounded.
A cell of a reference side is the same in the basic structure as that of the memory side and has one select transistor 102r and one MTJ element 104r. The resistance value of the MTJ element 104r of the cell of the reference side is, e.g., the medium value between a resistance value of the MTJ element 104 of the memory side in the high resistance state and a resistance value thereof in the low resistance state.
When the select transistor 102 is turned on, and a current is flowed from the current source 106 to the MTJ element 104, a voltage corresponding to memorized information (resistance value) written in the MTJ element 104 to the terminal of the MTJ element 104 on the current source side 106. That is, when the MTJ element 104 is in the high resistance state, a high level voltage is outputted, and a low level voltage is outputted when the MTJ element 104 is in the low resistance state. This voltage outputted from the cell of the memory side and the cell of the reference side is amplified by a sense amplifier (not shown) connected to the next stage and compared, whereby the memorized information in the cell of the memory side can be read.
The read circuit of the magnetic memory device shown in FIG. 18 is described in, e.g., M. Durlam et al., “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects”, 2002 Symposium on VLSI Circuits Digest of Technical Papers.
The magnetic memory device shown in FIG. 19 has a memory cell 100 formed of two select transistors 102a, 102b and two MTJ elements 104, 104b (2T-2MTJ type). In the MTJ elements 104a, 104b, complementary resistance states are written. That is, a high resistance state is written in one of the MTJ elements 104a, 104b and a low resistance state is written in the other.
The select transistor 102a and the MTJ element 104a, and the select transistor 102b and the MTJ element 104b are respectively serially connected. The select transistor 102a and the select transistor 102b are connected to each other at the terminals which are opposite to the terminals connected to the MTJ elements 104a, 104b. The other terminal of the MTJ element 104a is connected to a constant voltage Vd, and the other terminal of the MTJ element 104b is grounded.
When the select transistors 102a, 102b are turned on, a current flows through the serial connection of the MTJ element 104a, the select transistor 102a, the select transistor 102b and the MTJ element 104b. Thus, voltages corresponding to memorized information written in the MTJ elements 104a, 104b are outputted to the connection node between the select transistor 102a and the select transistor 102b. That is, due to the resistance voltage division between the MTJ element 104a and the MTJ element 104b, when the MTJ element 104a is in the low resistance state, and the MTJ element 104b is in the high resistance state, a high level voltage is outputted, and a low level voltage is outputted when the MTJ element 104a is in the high resistance state, and the MTJ element 104b is in the low resistance state. A voltage Vsig outputted from the cell of the memory side and a reference voltage Vref are amplified by a sense amplifier (not shown) connected to the next stage and compared, whereby the memorized information in the cell of the memory side can be read.
The read circuit of the magnetic memory device shown in FIG. 19 is described in, e.g., T. Inaba et al., “Resistance Ration Read (R3) Architecture for a Burst Operated 1.5V MRAM Macro”, IEEE 2003 Custom Integrated Circuits Conference, pp. 399-402.
The magnetic memory device shown in FIG. 20 has a memory cell 100 of 1T-1MTJ type including a select transistor 102 and an MTJ element 104. On the reference side, a cell including a high resistance MTJ element 104h and a cell including a low resistance MTJ element 104L are formed. A current mirror sense amplifier 110 as the amplifier of the first stage is connected to the cell of the memory side and the cells of the reference side via a clamp transistor 108.
When a current flowing in the MTJ element 104H is IH, and a current flowing in the MTJ element 104L is IL, currents supplied from the current mirror sense amplifier 110 to three signal lines connected thereto are respectively (IH+IL)/2. Accordingly, a voltage at the node N1 of the memory side and a voltage at the node N2 of the reference side are amplified by an amplifier (not shown) connected to the next stage and compared, whereby memorized information in the cell of the memory side can be read.
The read circuit of the magnetic memory device shown in FIG. 20 is described in, e.g., J. Nahas et al., “A 4 Mb 0.18-micron 1T1MTJ Toggle MRAM Memory”, 2004 IEEE International Solid-State Circuits Conference, pp. 44-45.